In this blog post, we will create a Verilog module named Hex to 7 segment decoder that performs this conversion. The module takes a 4-bit input and produces a 7-bit output to drive a 7-segment display.
Converting a 4-bit hexadecimal value to a 7-segment display output is a common task in digital design, especially when working with embedded systems and FPGA projects.
What is Hex to 7 segment decoder
A Hex to 7-segment decoder is a digital circuit that converts a 4-bit hexadecimal input (ranging from 0 to F) into signals that can drive a 7-segment display. The 7-segment display is commonly used in digital clocks, calculators, and other devices to display numerical digits.
Understanding the 7-Segment Display
For this project, we are using a 7-segment display with a common anode configuration. In a common anode display, all the anodes of the LEDs are connected together while the cathodes are individually connected to the controller.
In the common-anode case, an output 0 will turn on a segment and an output 1 will turn it off.
For a better understanding of the connection and total number of segments available on the basys3 FPGA board, please refer to this Document.
To get the most optimal boolean logic expression, refer to Chapter 9 of this Document. This will help you solve the K-map and further reduce the expression.
Verilog Code: Hex to 7 segment decoder
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`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // ////////////////////////////////////////////////////////////////////////////////// module hex7seg( input[3:0] i, output [6:0]seg ); assign i3 = i[3]; assign i2 = i[2]; assign i1 = i[1]; assign i0 = i[0]; assign seg[6] = (~i3 & ~i2 & ~i1 & i0) | (~i3 & i2 & ~i1 & ~i0) | (i3 & ~i2 & i1 & i0) | (i3 & i2 & ~i1 & i0); //{1,4,b,d} /// a segment assign seg[5] = (~i3 & i2 & ~i1 & i0) | (~i3 & i2 & i1 & ~i0) | (i3 & ~i2 & i1 & i0) | (i3 & i2 & ~i1 & ~i0) | (i3 & i2 & i1 & ~i0) | (i3 & i2 & i1 & i0); //seg b//{5,6,b,c,e,f} //b assign seg[4] = (~i3 & ~i2 & i1 & ~i0) | (i3 & i2 & ~i1 & ~i0) | (i3 & i2 & i1 & ~i0) | (i3 & i2 & i1 & i0); //seg c {2,c,e,f} assign seg[3] = (~i3 & ~i2 & ~i1 & i0) | (~i3 & i2 & ~i1 & ~i0) | (~i3 & i2 & i1 & i0) | (i3 & ~i2 & i1 & ~i0) | (i3 & i2 & i1 & i0); //seg d(1,4,7,a,f) assign seg[2] = (~i3 & ~i2 & ~i1 & i0) | (~i3 & ~i2 & i1 & i0) | (~i3 & i2 & ~i1 & ~i0) | (~i3 & i2 & ~i1 & i0) | (~i3 & i2 & i1 & i0) | (i3 & ~i2 & ~i1 & i0);//seg e{1,3,4,5,7,9} assign seg[1] = (~i3 & ~i2 & ~i1 & i0) | (~i3 & ~i2 & i1 & ~i0) | (~i3 & ~i2 & i1 & i0) | (~i3 & i2 & i1 & i0) | (i3 & i2 & ~i1 & i0); //seg g(1,2,3,7,d) assign seg[0] = (~i3 & ~i2 & ~i1 & ~i0) | (~i3 & ~i2 & ~i1 & i0) | (~i3 & i2 & i1 & i0) | (i3 & i2 & ~i1 & ~i0);// seg f(0,1,7,c) endmodule |
Code Explanation
The hex7seg module accepts a 4-bit input (i) representing a hexadecimal digit and producing a 7-bit output (seg) that drives a 7-segment display to show the corresponding hexadecimal value.
Detailed Explanation
- Module Declaration:
module hex7seg(input [3:0] i, output [6:0] seg);- The module has a 4-bit input (
i) and a 7-bit output (seg).
- Input Bit Assignment:
- For clarity, each bit of the input
iis assigned to a separate wire (i3,i2,i1,i0).
- For clarity, each bit of the input
- Segment Logic:
- Each segment (
seg[0]toseg[6]) is driven by a combination of the input bits. The logic for each segment is derived from the truth table of a 7-segment display for hexadecimal digits.
- Each segment (
Functionality
The 7-segment display has 7 segments, labeled a to g, which are mapped to seg[6] to seg[0] respectively. The segments are controlled based on the input value i (ranging from 0 to 15 in hexadecimal). The logic equations ensure that the correct segments are lit up to display the hexadecimal digit
Verilog testbench code : Hex to 7 segment decoder
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`timescale 1ns / 1ps module hex7seg_tb; // Inputs reg [3:0] i; // Outputs wire [6:0] seg; // Instantiate the hex7seg module hex7seg uut ( .i(i), .seg(seg) ); initial begin // Initialize input i = 4'b0000; // Wait for the global reset #10; // Test all possible 4-bit input values (0 to 15) $display("Testing all possible 4-bit values"); i = 4'b0000; #10; $display("i = %b, seg = %b", i, seg); i = 4'b0001; #10; $display("i = %b, seg = %b", i, seg); i = 4'b0010; #10; $display("i = %b, seg = %b", i, seg); i = 4'b0011; #10; $display("i = %b, seg = %b", i, seg); i = 4'b0100; #10; $display("i = %b, seg = %b", i, seg); i = 4'b0101; #10; $display("i = %b, seg = %b", i, seg); i = 4'b0110; #10; $display("i = %b, seg = %b", i, seg); i = 4'b0111; #10; $display("i = %b, seg = %b", i, seg); i = 4'b1000; #10; $display("i = %b, seg = %b", i, seg); i = 4'b1001; #10; $display("i = %b, seg = %b", i, seg); i = 4'b1010; #10; $display("i = %b, seg = %b", i, seg); i = 4'b1011; #10; $display("i = %b, seg = %b", i, seg); i = 4'b1100; #10; $display("i = %b, seg = %b", i, seg); i = 4'b1101; #10; $display("i = %b, seg = %b", i, seg); i = 4'b1110; #10; $display("i = %b, seg = %b", i, seg); i = 4'b1111; #10; $display("i = %b, seg = %b", i, seg); // End of simulation $finish; end endmodule |
Constraints file : Basys3 board
Modify this file when you are preparing for synthesis, implementation, and bitstream generation. Be sure to activate the necessary properties when using it. You can ignore this file for simulation purposes.
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## This file is a general .xdc for the Basys3 rev B board ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock signal set_property PACKAGE_PIN W5 [get_ports clkin] set_property IOSTANDARD LVCMOS33 [get_ports clkin] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clkin] ## Switches set_property PACKAGE_PIN V17 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] set_property PACKAGE_PIN V16 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] set_property PACKAGE_PIN W16 [get_ports {sw[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] set_property PACKAGE_PIN W17 [get_ports {sw[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] set_property PACKAGE_PIN W15 [get_ports {sw[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] set_property PACKAGE_PIN V15 [get_ports {sw[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] set_property PACKAGE_PIN W14 [get_ports {sw[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] set_property PACKAGE_PIN W13 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] set_property PACKAGE_PIN V2 [get_ports {sw[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] set_property PACKAGE_PIN T3 [get_ports {sw[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] set_property PACKAGE_PIN T2 [get_ports {sw[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] set_property PACKAGE_PIN R3 [get_ports {sw[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] set_property PACKAGE_PIN W2 [get_ports {sw[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] set_property PACKAGE_PIN U1 [get_ports {sw[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] set_property PACKAGE_PIN T1 [get_ports {sw[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] set_property PACKAGE_PIN R2 [get_ports {sw[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] ## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] set_property PACKAGE_PIN V13 [get_ports {led[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] set_property PACKAGE_PIN V3 [get_ports {led[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] set_property PACKAGE_PIN W3 [get_ports {led[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] set_property PACKAGE_PIN U3 [get_ports {led[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] set_property PACKAGE_PIN P3 [get_ports {led[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] set_property PACKAGE_PIN N3 [get_ports {led[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] set_property PACKAGE_PIN P1 [get_ports {led[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] set_property PACKAGE_PIN L1 [get_ports {led[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] ##7 segment display set_property PACKAGE_PIN W7 [get_ports {seg[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] set_property PACKAGE_PIN W6 [get_ports {seg[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] set_property PACKAGE_PIN U8 [get_ports {seg[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] set_property PACKAGE_PIN V8 [get_ports {seg[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] set_property PACKAGE_PIN U5 [get_ports {seg[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] set_property PACKAGE_PIN V5 [get_ports {seg[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] set_property PACKAGE_PIN U7 [get_ports {seg[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] set_property PACKAGE_PIN V7 [get_ports dp] set_property IOSTANDARD LVCMOS33 [get_ports dp] set_property PACKAGE_PIN U2 [get_ports {an[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] set_property PACKAGE_PIN U4 [get_ports {an[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] set_property PACKAGE_PIN V4 [get_ports {an[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] set_property PACKAGE_PIN W4 [get_ports {an[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] ##Buttons set_property PACKAGE_PIN U18 [get_ports btnC] set_property IOSTANDARD LVCMOS33 [get_ports btnC] #set_property PACKAGE_PIN T18 [get_ports btnU] #set_property IOSTANDARD LVCMOS33 [get_ports btnU] #set_property PACKAGE_PIN W19 [get_ports btnL] #set_property IOSTANDARD LVCMOS33 [get_ports btnL] set_property PACKAGE_PIN T17 [get_ports btnR] set_property IOSTANDARD LVCMOS33 [get_ports btnR] #set_property PACKAGE_PIN U17 [get_ports btnD] #set_property IOSTANDARD LVCMOS33 [get_ports btnD] ##Pmod Header JA ##Sch name = JA1 #set_property PACKAGE_PIN J1 [get_ports {JA[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] ##Sch name = JA2 #set_property PACKAGE_PIN L2 [get_ports {JA[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] ##Sch name = JA3 #set_property PACKAGE_PIN J2 [get_ports {JA[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] ##Sch name = JA4 #set_property PACKAGE_PIN G2 [get_ports {JA[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] ##Sch name = JA7 #set_property PACKAGE_PIN H1 [get_ports {JA[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] ##Sch name = JA8 #set_property PACKAGE_PIN K2 [get_ports {JA[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] ##Sch name = JA9 #set_property PACKAGE_PIN H2 [get_ports {JA[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] ##Sch name = JA10 #set_property PACKAGE_PIN G3 [get_ports {JA[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] ##Pmod Header JB ##Sch name = JB1 #set_property PACKAGE_PIN A14 [get_ports {JB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] ##Sch name = JB2 #set_property PACKAGE_PIN A16 [get_ports {JB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] ##Sch name = JB3 #set_property PACKAGE_PIN B15 [get_ports {JB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] ##Sch name = JB4 #set_property PACKAGE_PIN B16 [get_ports {JB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] ##Sch name = JB7 #set_property PACKAGE_PIN A15 [get_ports {JB[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] ##Sch name = JB8 #set_property PACKAGE_PIN A17 [get_ports {JB[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] ##Sch name = JB9 #set_property PACKAGE_PIN C15 [get_ports {JB[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] ##Sch name = JB10 #set_property PACKAGE_PIN C16 [get_ports {JB[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] ##Pmod Header JC ##Sch name = JC1 #set_property PACKAGE_PIN K17 [get_ports {JC[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] ##Sch name = JC2 #set_property PACKAGE_PIN M18 [get_ports {JC[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] ##Sch name = JC3 #set_property PACKAGE_PIN N17 [get_ports {JC[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] ##Sch name = JC4 #set_property PACKAGE_PIN P18 [get_ports {JC[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] ##Sch name = JC7 #set_property PACKAGE_PIN L17 [get_ports {JC[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] ##Sch name = JC8 #set_property PACKAGE_PIN M19 [get_ports {JC[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] ##Sch name = JC9 #set_property PACKAGE_PIN P17 [get_ports {JC[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] ##Sch name = JC10 #set_property PACKAGE_PIN R18 [get_ports {JC[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] ##Pmod Header JXADC ##Sch name = XA1_P #set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] ##Sch name = XA2_P #set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] ##Sch name = XA3_P #set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] ##Sch name = XA4_P #set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] ##Sch name = XA1_N #set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] ##Sch name = XA2_N #set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] ##Sch name = XA3_N #set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] ##Sch name = XA4_N #set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] ##VGA Connector #set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] #set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] #set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] #set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] #set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] #set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] #set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] #set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] #set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] #set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] #set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] #set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] #set_property PACKAGE_PIN P19 [get_ports Hsync] #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] #set_property PACKAGE_PIN R19 [get_ports Vsync] #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] ##USB-RS232 Interface #set_property PACKAGE_PIN B18 [get_ports RsRx] #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] #set_property PACKAGE_PIN A18 [get_ports RsTx] #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] ##USB HID (PS/2) #set_property PACKAGE_PIN C17 [get_ports PS2Clk] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] #set_property PULLUP true [get_ports PS2Clk] #set_property PACKAGE_PIN B17 [get_ports PS2Data] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] #set_property PULLUP true [get_ports PS2Data] ##Quad SPI Flash ##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the ##STARTUPE2 primitive. #set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] #set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] #set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] #set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] #set_property PACKAGE_PIN K19 [get_ports QspiCSn] #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] |
Schematic : Hex to 7 segment decoder
Simulation: Hex to 7 segment decoder
Conclusion
In this post, we designed a Verilog module to convert a 4-bit hexadecimal input to a 7-segment display output, specifically for a common anode 7-segment display. This module is particularly useful in various digital design applications where hexadecimal numbers need to be displayed on 7-segment displays, such as in FPGA-based projects.
We also provided a testbench to verify the functionality of the hex7seg module. Using the Basys3 FPGA, you can easily integrate this module into your projects to display hexadecimal values on the onboard 7-segment display. Feel free to adapt and modify this module as needed for your specific requirements. Happy coding with your Basys3 FPGA!
Stay tuned for more insightful articles on digital design and Verilog programming!
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