Sign Changer Verilog code Using Vivado @ Xilinx Basys3 FPGA

In digital design, changing the sign of a number is a common operation, especially in arithmetic and signal processing applications. This blog post will walk you through implementing a sign changer module in Verilog. We’ll explore the functionality, the code, and how it leverages a few fundamental components like an 8-bit adder and a 2-to-1 multiplexer.

Table of Contents

What is Sign Changer

The sign changer module takes an 8-bit input a and a control signal sign. Based on the value of the sign, it either outputs the original value of a or its two’s complement, effectively changing its sign.

The module also provides an overflow flag to indicate if the operation resulted in an overflow.

Verilog Code: Sign Changer




`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

module SignChanger(
    input [7:0] a,
    input sign,
    output[7:0] b,
    output overflow
    );
    wire [7:0] c;
    wire w;
    eightbitadder add (.A(~a), .B(8'b00000001), .Cin(8'b0), .S(c), .Cout(w));
    twotoonemux mux (.i0(a), .i1(c), .s(sign), .out(b));
    assign overflow = a[7] & ~(|a[6:0]) & sign;
    
    
endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

module SignChanger(

input [7:0] a,

input sign,

output[7:0] b,

output overflow

);

wire [7:0] c;

wire w;

eightbitadder add (.A(~a), .B(8'b00000001), .Cin(8'b0), .S(c), .Cout(w));

twotoonemux mux (.i0(a), .i1(c), .s(sign), .out(b));

assign overflow = a[7] & ~(|a[6:0]) & sign;

endmodule

Code Explanation

Module Declaration and Ports:
- input [7:0] a: 8-bit input number.
- input sign: Control signal to determine if the sign should be changed.
- output [7:0] b: 8-bit output number with the potentially changed sign.
- output overflow: Output flag to indicate overflow.
Internal Signals:
- wire [7:0] c: Internal wire to store the result of the two’s complement operation.
- wire w: Internal wire to capture the carry-out from the adder.
8-bit Adder Instantiation:
- The eightbitadder instance computes the two’s complement of a by adding 1 to the bitwise NOT of a.
2-to-1 Mux Instantiation:
- The twotoonemux instance selects between the original input a and its two’s complement c based on the sign control signal. If sign is 0, the output b is a; if sign is 1, the output b is c.
Overflow Detection:
- The overflow logic checks if the input a is the smallest negative number in 2’s complement form (10000000) and if the sign control signal is set. If both conditions are true, it sets the overflow flag.

Verilog testbench code : Sign Changer




`timescale 1ns / 1ps

module SignChanger_tb;

    reg [7:0] a;
    reg sign;
    wire [7:0] b;
    wire overflow;

    // Instantiate the SignChanger module
    SignChanger uut (
        .a(a),
        .sign(sign),
        .b(b),
        .overflow(overflow)
    );

    initial begin
        // Test case 1: Positive number, no sign change
        a = 8'd42;
        sign = 1'b0;
        #10;
        $display("a = %d, sign = %b, b = %d, overflow = %b", a, sign, b, overflow);
        
        // Test case 2: Positive number, sign change
        a = 8'd42;
        sign = 1'b1;
        #10;
        $display("a = %d, sign = %b, b = %d, overflow = %b", a, sign, b, overflow);
        
        // Test case 3: Negative number, no sign change
        a = 8'b11110110;  // -10 in two's complement
        sign = 1'b0;
        #10;
        $display("a = %d, sign = %b, b = %d, overflow = %b", a, sign, b, overflow);
        
        // Test case 4: Negative number, sign change
        a = 8'b11110110;  // -10 in two's complement
        sign = 1'b1;
        #10;
        $display("a = %d, sign = %b, b = %d, overflow = %b", a, sign, b, overflow);
        
        // Test case 5: Smallest negative number, sign change
        a = 8'b10000000;  // -128 in two's complement
        sign = 1'b1;
        #10;
        $display("a = %d, sign = %b, b = %d, overflow = %b", a, sign, b, overflow);

        // End of test
        $finish;
    end

endmodule

`timescale 1ns / 1ps

module SignChanger_tb;

reg [7:0] a;

reg sign;

wire [7:0] b;

wire overflow;

// Instantiate the SignChanger module

SignChanger uut (

.a(a),

.sign(sign),

.b(b),

.overflow(overflow)

);

initial begin

// Test case 1: Positive number, no sign change

a = 8'd42;

sign = 1'b0;

#10;